PCS2P3805E Datasheet, PDF (7/11 Pages) PulseCore Semiconductor – 3.3V CMOS Dual 1-To-5 Clock Driver

September 2006
rev 0.3
Test Circuits and Waveforms
ENABLE
CONTROL
INPUT
t_PZL
OUTPUT
NORMALLY ^SWITCH
LOW ^CLOSED
OUTPUT
NORMALLY
HIGH
t_PZH
SWITCH
OPEN
DISABLE
V_OH
1.5V
t_PHZ
t_PLZ
0.3V
1.5V
V_OL
0.3V
Enable and Disable Times
3V
1.5V
0V
V_OH
V_OL
V_OH
V_OL
Note: 1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
PCS2P3805E
INPUT
Package 1
OUTPUT
Package 2
OUTPUT
t_PLH1
t_PHL1
t_SK(PP)
t_SK(PP)
t_PLH2
t_PHL2
t_SK(PP) = | t_PLH2 - t_PLH1 | or | t_PHL2 - t_PHL1 |
3V
1.5V
0V
V_OH
1.5V
V_OL
V_OH
1.5V
V_OL
Part-to- Part Skew
Note: Part-to- Part Skew is for package and speed grade.
INPUT
OUTPUT
t_PLH
t_R
t_PHL
t_F
3V
1.5V
0V
V_OH
2.0V
1.5V
0.8V _VOL
Propagation Delay
INPUT
OUTPUT
t_PLH
t_PHL
t_SK(P) = | t_PLH - t_PLH |
Pulse Skew
3V
1.5V
0V
V_OH
1.5V
V_OL
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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