PCS2I9942P Datasheet, PDF (6/10 Pages) PulseCore Semiconductor – Low Voltage 1:18 Clock Distribution Chip

September 2006
rev 0.4
T_J,MAX should be selected according to the MTBF
system requirements and Table 8. R_thja can be derived
from Table 9. The R_thja represent data based on 1S2P
boards, using 2S2P boards will result in lower thermal
impedance than indicated below.
Table 9. Thermal package impedance of the
32LQFP
Convection, R_thja (1P2S
R_thja (2P2S
LFPM
board), °C/W board), °C/W
Still air
86
61
100 lfpm
76
56
200 lfpm
71
54
300 lfpm
68
53
400 lfpm
66
52
500 lfpm
60
49
PCS2I9942P
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given
application conditions. The following eight derating charts
describe the safe frequency operation range for the
PCS2I9942P. The charts were calculated for a maximum
tolerable die junction temperature of 110°C (120°C),
corresponding to an estimated MTBF of 9.1 years
(4 years), a supply voltage of 3.3V and series terminated
transmission line or capacitive loading. Depending on a
given set of these operating conditions and the available
device convection a decision on the maximum operating
frequency can be made.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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