PCS3P2537A Datasheet, PDF (4/7 Pages) PulseCore Semiconductor – Low Power Peak EMI Reduction IC

February 2008
rev 0.2
Typical Application Schematic
CLKIN / XIN _{1 CLKIN / XIN}
VDD ⁸
VDD
0Ω
0Ω
2 _XOUT
3 SSON
4 _NC
NC 7
ModOUT 6
GND 5
PCS3P2537A
VDD
0.01uF
Note: Refer to Pin Description table for Functionality Details
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
• Dedicated VDD and GND planes.
• The device must be isolated from system power supply noise. A 0.01µF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be
used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via
should be kept as short as possible. All the VDD pins should have decoupling capacitors.
• In an optimum layout all components are on the same side of the board, minimizing vias through other
signal layers.
A typical layout is shown in the figure
CLKIN
XOUT
SSON
NC
As short
as possible
VDD
NC
MoGdNoDut
GND
Low Power Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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