PCS5I961P Datasheet, PDF (2/14 Pages) PulseCore Semiconductor – Low Voltage Zero Delay Buffer

November 2006
rev 0.3
Pin Configuration
PCS5I961P
Q5
Q4
Q3
GND
Q2
Q1
Q0
VCC
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
P^PC^CS^S55^I9I⁶9¹6^C1P
13
29
12
30
11
31
10
32
9
1 2 3 4 5 67 8
VCC
Q12
Q13
Q14
GND
Q15
Q16
QFB
Figure 2. PCS5I961P 32-Lead Package Pinout (Top View)
Table 1: Pin Configuration
Pin #
2,3
Pin Name
PCLK, ^{¯P¯C¯L¯K¯}
7
FB_IN
4
6
31,30,29,27,26,25,23,22,21
,19,18,17,15,14,13,11,10
F_RANGE
O¯¯E
Q0 - Q16
9
QFB
1,12,20,28
GND
5
VCCA
8,16,24,32
VCC
I/O
Input
Input
Input
Input
Output
Output
Supply
Supply
Supply
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
Power
Power
Function
PLL reference clock signal
PLL feedback signal input, connect to a QFB
output
PLL frequency range select
Output enable/disable
Clock outputs
PLL feedback signal output, connect to a
FB_IN
Negative power supply
PLL positive power supply (analog power
supply). The PCS5I961P requires an
external RC filter for the analog power
supply pin VCCA. Please see applications
section for details.
Positive power supply for I/O and core
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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