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ASM2P2310A Datasheet, PDF (2/11 Pages) PulseCore Semiconductor – 2.5-V TO 3.3-V High-Performance Clock Buffer
November 2006
rev 0.3
Pin Configuration
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
Pin Name
GND
VDD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
1G
12
2Y4
13
2G
14
VDD
15
VDD
16
2Y3
17
2Y2
18
GND
19
GND
20
2Y1
21
2Y0
22
VDD
23
VDD
24
CLK
ASM2P2310A
GND
VDD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
1G
2Y4
1
24
2
23
3
22
4
21
5
20
6 ASM2P2310A 19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
VDD
VDD
2Y0
2Y1
GND
GND
2Y2
2Y3
VDD
VDD
2G
Type
P
P
O
O
O
P
P
O
O
P
I
O
I
P
P
O
O
P
P
O
O
P
P
I
Description
Ground Pin
DC Power supply, 2.3 V – 3.6V
Buffered Output Clock
Buffered Output Clock
Buffered Output Clock
Ground Pin
Ground Pin
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
Output enable control for 1Y[0:4] outputs. This output enable is active-high,
meaning the 1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic
high.
Buffered Output Clock
Output enable control for 2Y[0:4] outputs. This output enable is active-high,
meaning the 2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic
high.
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Buffered Output Clock
Buffered Output Clock
Ground Pin
Ground Pin
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Input reference frequency
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
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