PCS5I9772 Datasheet, PDF (1/15 Pages) PulseCore Semiconductor – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

September 2006
rev 0.4
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
PCS5I9772
Features
• Output frequency range: 8.33MHz to 200MHz
• Input frequency range: 6.25MHz to 125MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2% max Output duty cycle variation
• 12 clock outputs: drive up to 24 clock lines
• One feedback output
• Three reference clock inputs: crystal or LVCMOS
• 300pS max output-output skew
• Phase-locked loop (PLL) bypass mode
• ‘SpreadTrak’
• Output enable/disable
• Pin-compatible with CY29772, MPC9772 and
MPC972
• Industrial temperature range: -40°C to +85°C
• 52 pin 1.0 mm TQFP package
• RoHS Compliance
Functional Description
The PCS5I9772 is a low-voltage high-performance
200MHz PLL-based zero delay buffer, designed for
high-speed clock-distribution applications.
Block Diagram
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
TCLK0
0
TCLK1
1
TCLK_SEL
FB_IN
FB_SEL2
Phase
Detector
VCO
LPF
The PCS5I9772 features one on-chip crystal oscillator and
two LVCMOS reference clock inputs and provides 12
outputs partitioned in three banks of four outputs each.
Each bank divides the VCO output per SEL(A:C) settings,
see Functional Table.
These dividers allow output to input ratios of 8:1, 6:1, 5:1,
4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50Ω series or
parallel-terminated transmission lines. For series-
terminated transmission lines, each output can drive one or
two traces, giving the device an effective fanout of 1:24.
The PLL is ensured stable given that the VCO is configured
to run between 200MHz and 500MHz. This allows a wide
range of output frequencies from 8MHz to 200MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
0
DQ
Sync
Frz
QA0
QA1
1
QA2
QA3
DQ
Sync
Frz
QB0
QB1
QB2
QB3
MR#/OE
SELA(0,1)
SELB(0,1)
SELC(0,1)
FB_SEL(0,1)
SCLK
SDATA
INV_CLK
Power-On
Reset
2
2
2
2
/4,/6,/8,/12
/4,/6,/8,/10
/2/4,/6,/8
/4,/6,/8,/10
Sync Pulse
Data Generator
0
/2 1
Output Disable
12
Circuitry
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
QC0
QC1
QC2
QC3
FB_OUT
SYNC
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: [phone] • Fax: [phone]
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.