PCS2P5T9050A Datasheet, PDF (1/10 Pages) PulseCore Semiconductor – 2.5V Single Data Rate1:5 Clock Buffer Terabuffer

November 2006
rev 0.2
PCS2P5T9050A
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Features
• Optimized for 2.5V LVTTL
• Guaranteed Low Skew < 25pS (max)
• Very low duty cycle distortion< 300pS (max)
• High speed propagation delay < 1.8nS. (max)
• Up to 200MHz operation
• Very low CMOS power levels
• Hot Insert able and over-voltage tolerant inputs
• 1:5 fan-out buffer
• 2.5V Supply Voltage
• Available in TSSOP Package
Functional Description
Block Diagram
GL
G
A
The PCS2P5T9050A 2.5V single data rate (SDR) clock
buffer is a single-ended input to five single-ended outputs
buffer built on advanced metal CMOS technology. The
SDR clock buffer fan-out from a single input to five
single-ended outputs reduces the loading on the preceding
driver and provides an efficient clock distribution network.
Multiple power and grounds reduce noise.
Applications:
PCS2P5T9050A is targeted towards Clock and signal
distribution applications.
OUTPUT
Q1
CONTROL
OUTPUT
Q2
CONTROL
OUTPUT
Q3
CONTROL
OUTPUT
Q4
CONTROL
OUTPUT
Q5
CONTROL
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: [phone] • Fax: [phone]
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.