PCS2P3805A Datasheet, PDF (1/12 Pages) PulseCore Semiconductor – 3.3V CMOS Buffer Clock Driver

September 2006
rev 0.3
PCS2P3805A
3.3V CMOS Buffer Clock Driver
Features
• Advanced CMOS Technology
• Guaranteed low skew < 500pS (max.)
• Very low duty cycle distortion < 1.0nS (max)
• Very low CMOS power levels
• TTL compatible inputs and outputs
• Inputs can be driven from 3.3V or 5V components
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• "Heartbeat" monitor output
• V_CC = 3.3V ± 0.3V
• Available in SSOP, SOIC and QSOP Packages
Functional Description
The PCS2P3805A is a 3.3V, non-inverting clock driver built
using advanced CMOS technology. The device consists of
two banks of drivers, each with a 1:5 fanout and its own
output enable control. The device has a "heartbeat" monitor
for diagnostics and PLL driving. The MON output is
identical to all other outputs and complies with the output
specifications in this document. The PCS2P3805A offers
low capacitance inputs.
The PCS2P3805A is designed for high speed clock
distribution where signal quality and skew are critical. The
PCS2P3805A also allows single point-to-point transmission
line driving in applications such as address distribution,
where one signal must be distributed to multiple receivers
with low skew and high signal quality.
Block Diagram
OE_A
IN_A
IN_B
OE_B
5
OA₁ – OA₅
5
OB₁ – OB₅
MON
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: [phone] • Fax: [phone]
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.