PCS2P20805A Datasheet, PDF (1/11 Pages) PulseCore Semiconductor – 2.5V CMOS Dual 1-To-5 Clock Driver

September 2006
rev 0.3
PCS2P20805A
2.5V CMOS Dual 1-To-5 Clock Driver
Features
• Advanced CMOS Technology
• Guaranteed low skew < 200pS (max.)
• Very low propagation delay < 2.5nS (max)
• Very low duty cycle distortion < 270pS (max)
• Very low CMOS power levels
• Operating frequency up to 166MHz
• TTL compatible inputs and outputs
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• "Heartbeat" monitor output
• V_CC = 2.5V ± 0.2V
• Available in SSOP and QSOP packages
Functional Description
The PCS2P20805A is a 2.5V Clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in this document. The PCS2P20805A offers low
capacitance inputs. The PCS2P20805A is designed for
high speed clock distribution where signal quality and skew
are critical. The PCS2P20805A also allows single point-to-
point transmission line driving in applications such as
address distribution, where one signal must be distributed
to multiple receivers with low skew and high signal quality.
Block Diagram
OE_A
IN_A
IN_B
OE_B
5
OA₁ – OA₅
5
OB₁ – OB₅
MON
Pin Diagram
V_CCA 1
OA₁ 2
OA₂ 3
OA₃ ⁴
GND_A 5
OA₄ ⁶
OA_{5 7}
GND_Q 8
OE_A ⁹
IN_A 10
PCS2P20805A
20 V_CCB
19 _OB1
18 _OB2
17 _OB3
16 _GNDB
15 _OB4
14 _OB5
13 _MON
12 _OEB
11 _INB
SSOP/ QSOP PACKAGE
TOP VIEW
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: [phone] • Fax: [phone]
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.