ASM3P622S01B Datasheet, PDF (1/12 Pages) PulseCore Semiconductor – Low Frequency Timing-Safe™ Peak EMI reduction IC

May 2007
rev 0.4
ASM3P622S01B/J
Low Frequency Timing-Safe™ Peak EMI reduction IC
General Features
• Low Frequency Clock distribution with Timing-
Safe™ Peak EMI Reduction
• Input frequency range: 4MHz - 20MHz.
• Zero input - output propagation delay
• Low-skew outputs
•
Output-output skew less than 250pS
•
Device-device skew less than 700pS
• Less than 200pS cycle-to-cycle jitter
• Available in 8pin, 150 mil SOIC, 4.4mm TSSOP
Package
• 3.3V Operation
• Industrial temperature range
• Advanced CMOS technology
• The First True Drop-in Solution
Functional Description
ASM3P622S01B/J is a versatile, 3.3V Zero-delay buffer
designed to distribute low frequency Timing-Safe™ clocks
with Peak EMI Reduction. The ASM3P622S01B/J is the
eight-pin version and accepts one reference input and
drives out one low-skew clock.
All parts have on-chip PLLs that lock to an input clock on
the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad, internal to the device.
Multiple ASM3P622S01B/J devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
The output has less than 200pS of cycle-to-cycle jitter. The
input and output propagation delay is guaranteed to be less
than 250pS, and the output-to-output skew is guaranteed to
be less than 250pS.
Refer “Spread Spectrum Control and Input-Output Skew
Table” for deviations and Input-Output Skew for
ASM3P622S01B/J devices.
Block Diagram
V_DD
SSON SS%
XIN/CLKIN
XOUT
Crystal
Oscillator
Reference
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Feedforward
Divider
CLKOUT
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: [phone] • Fax: [phone]
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.