ASM2P5T9070A Datasheet, PDF (1/9 Pages) PulseCore Semiconductor – 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer

November 2006
rev 0.2
ASM2P5T9070A
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Features
• Optimized for 2.5V LVTTL
• Guaranteed Low Skew < 25pS (max)
• Very low duty cycle distortion < 300pS (max)
• High speed propagation delay < 2nS. (max)
• Up to 200MHz operation
• Very low CMOS power levels
• Hot Insertable and over-voltage tolerant inputs
• 1:10 fanout buffer
• 2.5V Supply Voltage
• Available in TSSOP Package
Functional Description
The ASM2P5T9070A 2.5V single data rate (SDR) clock
buffer is a single-ended input to ten single-ended outputs
buffer built on advanced metal CMOS technology. The
SDR clock buffer fanout from a single input to ten single-
ended outputs reduces the loading on the preceding driver
and provides an efficient clock distribution network.
The ASM2P5T9070A has two output banks that can be
asynchronously enabled/disabled. Multiple power and
grounds reduce noise.
Applications:
ASM2P5T9070A is targeted towards Clock and signal
distribution applications.
Block Diagram
GL
G1
A
G2
OUTPUT
CONTROL
Q1
OUTPUT
CONTROL
Q2
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
OUTPUT
CONTROL
Q6
OUTPUT
CONTROL
Q7
OUTPUT
CONTROL
Q8
OUTPUT
Q9
CONTROL
OUTPUT
Q10
CONTROL
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: [phone] • Fax: [phone]
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.