PT6302_10 Datasheet, PDF (7/27 Pages) Princeton Technology Corp – VFD Driver/Controller IC with Character RAM

PT6302
RELATIONSHIP BETWEEN SEGMENT DRIVERS SGN AND ADN (ONE
DIGIT)
The following diagram best describes the relationship between the Segment Drivers -- SGn and ADn.
C0 AD1
C1 AD2
C0
SG1
C5
SG6
C10
SG11
C15
SG16
C20
SG21
C25
SG26
C30
SG31
C1
SG2
C6
SG7
C11
SG12
C16
SG17
C21
SG22
C26
SG27
C31
SG32
C2
SG3
C7
SG8
C12
SG13
C17
SG18
C22
SG23
C27
SG28
C32
SG33
C3
SG4
C8
SG9
C13
SG14
C18
SG19
C23
SG24
C28
SG29
C33
SG34
C4
SG5
C9
SG10
C14
SG15
C19
SG20
C24
SG25
C29
SG30
C34
SG35
DATA IS WRITTEN BY ADRAM.
THIS CORRESPONDS TO THE 2ND BYTE
DATA IS WRITTEN BY THE
CGRAM. THIS CORRESPONDS
TO THE 2ND BYTE
DATA IS WRIITEN BY THE CGRAM THIS
CORRESPONDS TO THE 3RD BYTE.
DATA IS WRIITEN BY THE CGRAM
THIS CORRESPONDS TO THE 6TH
DATA IS WRITTEN BY THE CGRAM
THIS CORRESPONDS TO THE 5TH
DATA IS WRITTEN BY THE CGRAM
THIS CORRESPONDS TO THE 4TH
DATA TRANSFER
The Display Control Command and the data are written by an 8-bit serial data transfer. Please refer to the Write Timing
Diagram below.
Note: When data is written into the RAM (DCRAM, ADRAM, CGRAM) in a continuous manner, the address are automatically incremented. Therefore
it is not necessary to specify the first byte of the 2nd and later bytes when writing the RAM data.
When the CSB pin is set to "LOW" Level, data transfer operation is enabled. 8 bits of data are sequentially inputted into
the DIN Pin (LSB first). The shift clock is inputted into CLKB pin and the shift register reads the data at rising edge of the
shift clock. The internal load signals are automatically generated and the data is written to each register and RAM. Thus,
it is not necessary to input load signals externally.
When the CSB Pin is set to "HIGH" Level, the data transfer operation is disabled. The data input when the CSB Pin
changes from "HIGH" to "LOW" is recognized in 8-bit units.
V2.1
7
August 2010