PT8300_10 Datasheet, PDF (5/19 Pages) Princeton Technology Corp – 16-Bit I/O Expander IC

Tel: [phone]
Fax: [phone]
URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
OPERATION
1. P0 to P15 are undefined when power is turned ON, but if /RESET is set to LOW, P0 to P7 are in
LOW state. If PULLUP pin is connected to VSS, P8 to P15 are floating. If PULLUP pin is
connected to VDD, P8 to P15 are in HIGH State.
2. The status of P0 to P15 is loaded to the Shift register 1 at the falling edge of LATCH/LATCHO.
3. At the falling edge of the CLK, the 16-bit serial output of the data loaded to the Shift register 1 (Shift
register 2) is sequentially performed from DO1(DO2).
4. At the rising edge of CLK, 16-bit serial data is written into the Shift register 1 (Shift register 2)
from DI1(DI2).
5. At the rising edge of the LATCH/LATCHO, the data written is outputted in a parallel manner to the
P0 to P15.
6. Shift Register 1 loads the data that is to be applied externally and the data with the latched content.
to the parallel output latch.
7. When the LATCH/LATCHO is activated after the arrival of CLK’s 16th bit, the parallel output
latch sends out P0 to P15 by storing the data that has been written into the Shift register 2. The
Shift Registers 1 and 2 continue the shift operation until the CLK’s 16th bit and the DO1 (DO2)
output serial data arrive.
8. Serial data is used to control the switching mode operation (input ↔ output) of P8 to P15. When
P8 to P15 operate as Output Pins, the PULLUP must be set to HIGH.
OPERATION TIMING DIAGRAM
/RESET
L ATC H/LATC HO
CL K/C LK O
DI1/DI2
DO 1/D O2
P0
P1
P15
1
2
3
4
5
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
DI0-1
DI1-1
D I 15-1
16
DI15
DO15
DI0
DI1
DI15
PT8300 V1.8
-5-
February, 2006