PT6552 Datasheet, PDF (4/22 Pages) Princeton Technology Corp – ½ Duty LCD Driver with On-Chip Key Input Function

PT6552
PIN CONFIGURATIONS
Pin Name
I/O
Function
Active
Segment outputs: Used to output the display data that is
SG1/P1 to SG4/P4
SG5 to SG43
O
transmitted over the serial data input. Pins SG1/P1 to
SG4/P2 can be used as general-purpose outputs
-
according to control data specification.
COM1
COM2
O
Common driver outputs.
The frame frequency fo is (fosc/512)Hz
-
Key scan outputs. When a key matrix is formed,
normally a diode will be attached to the key scan timing
KS1/SG44,
line to prevent shorts. However, since the output
KS2/SG45,
O transistor impedance is an unbalanced CMOS output, it
-
KS3 to KS6
will not be damaged if shorted. Pins KS1/SG44 and
KS2/SG45 can be used as segment outputs according
to control data specification.
KI1 to KI5
I
Key scan inputs: Pin with a built-in pull-down resistor.
H
OSC
I/O
Oscillator connection: Oscillator circuit can be formed by
connecting the pin to a resistor and a capacitor
-
V_SS
-
Power supply ground connected. Must be connected to
GND.
-
Reset input that re-initializes the LSI internal states.
During a reset, the display segments are turned off
/RES
I
forcibly regardless of the internal display data. All
internal key data is reset to low and the key scan
L
operation is disabled. However, serial data can input
during a reset.
V_DD
-
Power supply connection. A supply voltage of between
4.5 and 6.0V must be provided.
-
DO
O Serial data interface:
CE: Chip enable
-
CE
I
Connected to the controller. CLK: Synchronization
H
CLK
I
Since DO is an open-drain clock
output, it required a pull-up DI: Transfer data
DI
I
resistor.
DO: Output data
-
Handing when
unused
Open
Open
Open
GND
V_DD
-
GND
-
Open
GND
Pin No.
1 to 4
5 to 43
44
45
46
47
48 to 51
52 to 56
57
58
59
60
61
62
63
64
V1.3
4
July 2010