PT6324 Datasheet, PDF (4/4 Pages) Princeton Technology Corp – VFD Driver/Controller IC

PT6324
PIN DESCRIPTION
Pin Name
I/O
Description
Pin No.
CLK
I
Clock input pin
This pin reads serial data at the rising edge and outputs data at the falling edge.
1
Data input pin
DIN
I When this pin acts as input pin, serial data is inputted at the rising edge of the shift 2
clock (starting from the lower bit)
Serial interface strobe pin
STB
I The data input after the STB has fallen is processed as a command. When this in 3
is “HIGH”, CLK is ignored.
DOUT
Data output pin (N-channel, Open-drain)
O When this pin acts as output pin, serial data is outputted at the falling edge of the 4
shift clock (starting from the lower bit)
K1 to K2
I
Key data input pins
The data inputted to these pins is latched at the end of the display cycle.
5, 6
OSC
I
Oscillator input pin
A resistor is connected to this pin to determine the oscillation frequency.
7
GND
- Ground pin
8, 52
VDD
- Logic power supply
9, 51
SG1/KS1 to
SG16/KS16
O
High-voltage segment output pins
Also acts as the key source
10 to 25
SG17 to SG24 O High-voltage segment output pins
26 to 33
GR1 to GR16 O High-voltage grid output pins
34 to 49
VEE
- Pull-down level
50
V1.3
4