PE43705_14 Datasheet, PDF (9/18 Pages) Peregrine Semiconductor – UltraCMOS® RF Digital Step Attenuator

PE43705
Product Specification
Figure 4. Serial Timing Diagram
Bits can either be set to logic high or logic low
D[7] must be set to logic low
DI[6:0]
P/S
SI
CLK
LE
T
DISU
T
PSSU
D[0]
T
SISU
T
SIH
D[1]
D[2]
T
CLKL
D[3]
D[4]
D[5]
T
CLKH
D[6]
DO[6:0]
Figure 5. Latched Parallel/Direct Parallel
Timing Diagram
P/S
DI[6:0]
LE
DO[6:0]
T_PSSU
VALID
T_DISU
T_PSH
T_DIH
T_LEPW
VALID
T_DIPD
T_PD
Table 12. Serial Interface AC Characteristics
V_DD = 3.4V or 5.0V, -40°C < T_A < 105°C, unless otherwise specified
Parameter
Symbol Min Max Unit
Serial clock frequency
F_CLK
10 MHz
Serial clock HIGH time
T_CLKH
30
ns
Serial clock LOW time
T_CLKL
30
ns
Last serial clock rising edge setup
time to Latch Enable rising edge
T_LESU
10
ns
Latch enable min. pulse width
Serial data setup time
Serial data hold time
Parallel data setup time
Parallel data hold time
Address setup time
Address hold time
Parallel/serial setup time
Parallel/serial hold time
Digital register delay (internal)
T_LEPW
30
ns
T_SISU
10
ns
T_SIH
10
ns
T_DISU
100
ns
T_DIH
100
ns
T_ASU
100
ns
T_AH
100
ns
T_PSSU
100
ns
T_PSH
100
ns
T_PD
10
ns
Document No. DOC-47804-2 | www.psemi.com
D[7]
T
DIH
T
PSIH
T
LESU
T
LEPW
T
PD
VALID
Table 11. Latch and Clock Specifications
Latch Enable Shift Clock
Function
0
↑
Shift register clocked
↑
X
Contents of shift register
transferred to attenuator core
Table 13. Parallel and Direct Interface
AC Characteristics
V_DD = 3.4V or 5.0V, -40°C < T_A < 105°C, unless otherwise specified
Parameter
Symbol Min Max Unit
Latch enable minimum pulse
width
T_LEPW
30
ns
Parallel data setup time
Parallel data hold time
Parallel/serial setup time
Parallel/serial hold time
Digital register delay (internal)
Digital register delay (internal,
direct mode only)
T_DISU
100
ns
T_DIH
100
ns
T_PSSU
100
ns
T_PSIH
100
ns
T_PD
10 ns
T_DIPD
5
ns
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