PE43702 Datasheet, PDF (5/11 Pages) Peregrine Semiconductor – RF Digital Attenuator

PE43702
Product Specification
Table 5. Control Voltage
State
Low
Bias Condition
0 to +1.0 Vdc at 2 µA (typ)
High
+2.6 to +5 Vdc at 10 µA (typ)
Table 6. Latch and Clock Specifications
Latch Enable Shift Clock
Function
0
↑
Shift Register Clocked
↑
X
Contents of shift register
transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting
D6 D5 D4 D3 D2 D1 D0
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
Attenuation
Setting
RF1-RF2
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.75 dB
Table 9. Serial Attenuation Word Truth Table
Attenuation Word
Attenuation
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
Setting
RF1-RF2
L
L
L
L
L
L
L
L Reference I.L.
LL
L
L
L
L
L
H
0.25 dB
LL
L
L
L
L
H
L
0.5 dB
L
L
L
L
L
H
L
L
1 dB
L
L
L
L
H
L
L
L
2 dB
L
L
L
H
L
L
L
L
4 dB
L
L
H
L
L
L
L
L
8 dB
L
H
L
L
L
L
L
L
LHHHHHH
H
16 dB
31.75 dB
Table 8. Serial Register Map
MSB (last in)
LSB (first in)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D7
D6
D5
D4
D3
D2
D1
D0
Attenuation Word
Bit must be set to logic low
Attenuation Word is derived directly from the attenuation value. For example, to program the 12.5 dB state:
Attenuation Word: Multiply by 4 and convert to binary → 4 * 12.5 dB → 50 → 00110010
Serial Input: 00110010
Document No. 70-0244-04 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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