PE83336 Datasheet, PDF (3/12 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

PE83336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead
CQFJ)
Pin
Name
Interface
Mode
Type
Description
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
14
D₅
Parallel
Input
Parallel data bus bit5.
M₅
Direct
Input
M Counter bit5.
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the
8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
15
D₆
Parallel
Input
Parallel data bus bit6.
M₆
Direct
Input
M Counter bit6.
FSELS Serial
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
16
D₇
Parallel
Input
Parallel data bus bit7 (MSB).
Pre_en Direct
Input
Prescaler enable, active “low”. When “high”, F_in bypasses the prescaler.
17
GND
ALL
Ground.
18
FSELP Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A₀
Direct
Input
A Counter bit0 (LSB).
Serial
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
E_WR
19
Parallel
Input
Enhancement register write. D[7:0] are latched into the enhancement register on the rising
edge of E_WR.
A₁
Direct
Input
A Counter bit1.
20
M2_WR Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of
M2_WR.
A₂
Direct
Input
A Counter bit2.
21
Smode
Serial,
Parallel
Input
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0,
Smode=0).
A₃
Direct
Input
A Counter bit3 (MSB).
22
Bmode ALL
Input
Selects direct interface mode (Bmode=1).
23
V_DD
ALL
(Note 1) Same as pin 1.
24
M1_WR Parallel
Input
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of
M1_WR.
25
A_WR Parallel
Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of
A_WR.
26
Hop_WR
Serial,
Parallel
Input
Hop write. The contents of the primary register are latched into the secondary register on the
rising edge of Hop_WR.
27
F_in
ALL
Input
Prescaler input from the VCO. 3.0 GHz max frequency.
28
F_in
ALL
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 Ω resistor directly to the ground plane.
29
GND
ALL
Ground.
Document No. 70-0137-05 │ www.psemi.com
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
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