PE9309 Datasheet, PDF (2/6 Pages) Peregrine Semiconductor Corp. – 3.0 - 13.5 GHz Low Power UltraCMOS Divide-by-4 Prescaler

Figure 3. Pin Configuration (Top View)
VBYPS
1
VBYPS
2
RF IN 3
GND 4
9309
Top View
8
RBIAS
7
VDD
6 RF OUT
5 ^NC
Side View
GND
Table 2. Pin Descriptions
Pin No. Pin Name
Description
1
VBYPS
Prescaler Supply Bypass
2
VBYPS
Prescaler Supply Bypass
3
IN
RF Input
4
GND
Ground
5
NC
Not Connected
6
OUT
RF Output.
7
VDD
Supply Voltage
8
GND
RBIAS
GND
Frequency-Selecting Bias Resistor
Bottom of the package is Ground.
Connecting the bottom of the package to
ground is required
Table 3. Operating Ranges
Parameter
Min Typ Max Units
Supply Voltage (VDD)
2.45
2.6
2.75
V
Supply Current (IDD)
6
23
mA
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
©2007-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 6
PE9309
Product Specification
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max
VDD
TST
TOP
VESD
PINMAX
DC Supply voltage
Storage temperature
range
Operating temperature
range
ESD voltage (Human
Body Model)
Maximum input power
3.0
-65 150
-40
85
250
14
Units
V
°C
°C
V
dBm
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may reduce
reliability.
Device Functional Considerations
The PE9309 divides a 3.0 GHz to 13.5 GHz input
signal by four, producing a 750 MHz to 3.375 GHz
output signal. In order for the prescaler to work
properly, several conditions need to be adhered to.
It is crucial that pins 1, 2 and 7 be supplied with
bypass capacitors to ground. In addition, the output
signal (pins 6) needs to be ac coupled via an
external capacitor as shown in the test circuit in
Figure 5.
The input frequency range is selected by the value
of R_BIAS according to Figure 4.
The ground pattern on the board should be made as
wide as possible to minimize ground impedance.
The bottom of the package is the primary ground
connection and it needs to be soldered to the PCB
ground.
Figure 4. Frequency versus R_BIAS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
Lower Freq Lim
Optimal Freq Lim
Upper Freq Lim
5 10 15 20 25 30 35 40 45 50 55 60
RBIAS (KOhm)
Document No. 70-0241-05 │ UltraCMOS™ RFIC Solutions