PE43703MLI-Z Datasheet, PDF (1/15 Pages) Peregrine Semiconductor – 50 Ω RF Digital Attenuator 7-bit, 31.75 dB, 9 kHz - 6000 MHz VssEXT option

Product Specification
PE43703
50 Ω RF Digital Attenuator
Product Description
The PE43703 is a HaRP™-enhanced, high linearity, 7-bit RF
7-bit, 31.75 dB, 9 kHz - 6000 MHz
Vss_EXT option
Digital Step Attenuator (DSA). This highly versatile DSA
Features
covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB, or 1.0
dB steps. The customer can choose which step size and
 HaRP™-enhanced UltraCMOS™ device
associated specifications are best suited for their application.
The Peregrine 50Ω RF DSA provides multiple CMOS control
interfaces and an optional external Vss feature. It maintains
high attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power consumption.
E Performance does not change with VDD due to on-board
regulator. This next generation Peregrine DSA is available in a
5x5 mm 32-lead QFN footprint.
T 3 _{The PE43703 is manufactured on Peregrine’s UltraCMOS™}
1 ^{process, a patented variation of silicon-on-insulator (SOI)}
technology on a sapphire substrate, offering the performance
E ^{7 of GaAs with the economy and integration of conventional}
CMOS.
L ^{43 Figure 1. Package Type}
O ^{PE 32-lead 5x5x0.85 mm QFN Package}
 Attenuation options: 0.25 dB, 0.5 dB, or
1.0 dB steps to 31.75 dB
 0.25 dB monotonicity for ≤4.0 GHz
 0.5 dB monotonicity for ≤5.0 GHz
 1 dB monotonicity for ≤6.0 GHz
 High Linearity: Typical +59 dBm IIP3
 Excellent low-frequency performance
 Optional External Vss Control (Vss_EXT)
 3.3 V or 5.0 V Power Supply Voltage
 Fast switch settling time
 Programming Modes:
 Direct Parallel
 Latched Parallel
 Serial-Addressable: Program up to
eight addresses 000 - 111
 High-attenuation state @ power-up (PUP)
 CMOS Compatible
 No DC blocking capacitors required
S _{ITH Figure 2. Functional Schematic Diagram}
B ^W _{RF Input}
Switched Attenuator Array
RF Output
O ^{CE Parallel Control 7}
A ^{Serial In}
L _CLK
P _LE
RE^A0
Control Logic Interface
A1
A2
(optional)
P/S Vss_EXT
Document No. 70-0245-05 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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