PE4259 Datasheet, PDF (1/9 Pages) Peregrine Semiconductor Corp. – SPDT High Power UltraCMOS™ DC - 3.0 GHz RF Switch

Product Description
The PE4259 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from 10 MHz through 3000 MHz.
This reflective switch integrates on-board CMOS control logic
with a low voltage CMOS-compatible control interface, and can
be controlled using either single-pin or complementary control
inputs. Using a nominal +3-volt power supply voltage, a typical
input 1 dB compression point of +33.5 dBm can be achieved.
The PE4259 SPDT High Power RF Switch is manufactured on
Peregrine’s UltraCMOS™ process, a patented variation of
silicon-on-insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
RF1
ESD
RF2
ESD
Product Specification
PE4259
SPDT High Power UltraCMOS™
10 MHz – 3.0 GHz RF Switch
Features
• Single-pin or complementary CMOS
logic control inputs
• Low insertion loss: 0.35 dB at
1000 MHz, 0.5 dB at 2000 MHz
• Isolation of 30 dB at 1000 MHz, 20 dB
at 2000 MHz
• Typical input 1 dB compression point
of +33.5 dBm
• 1.8V minimum power supply voltage
• Ultra-small SC-70 package
Figure 2. Package Type SC-70
6-lead SC-70
CMOS
Control
Driver
CTRL CTRL or V_DD
Table 1. Electrical Specifications @ +25 °C, V_DD = 3 V (Z_S = Z_L = 50 Ω)
Parameter
Conditions
Minimum
Typical
Maximum
Units
Operation Frequency¹
Insertion Loss³
Isolation
Return Loss³
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
10 MHz
0.35
0.50
29
30
19
20
21
22
24
27
3000
0.45
0.60
MHz
dB
dB
dB
dB
dB
dB
‘ON’ Switching Time
50% CTRL to 0.1 dB of final value, 1 GHz
1.50
us
‘OFF’ Switching Time
50% CTRL to 25 dB isolation, 1 GHz
1.50
us
Video Feedthrough²
Input 1 dB Compression
Input IP3
1000 MHz @ 2.3 - 3.3 V
1000 MHz @ 1.8 - 2.3 V
2500 MHz @ 2.3 - 3.3 V
2500 MHz @ 1.8 - 2.3 V
1000 MHz, 20dBm input power
15
31.5
33.5
29.5
30.5
28.5
30.5
28
29
55
mVpp
dBm
dBm
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50 Ω test
set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
3. A tuning capacitor must be added to the application board to optimize the insertion loss and return loss performance. See Figure 6 for
details.
Document No. 70-0134-08 │ www.psemi.com
©2010 Peregrine Semiconductor Corp. All rights reserved.
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