PA5750 Datasheet, PDF (7/30 Pages) Protek Devices – Low Power Stereo Audio CODEC With Speaker and Headphone Amplifier.

ANALOG PRODUCTS DIVISION
PA5750
Low Power Stereo Audio CODEC
With Speaker and Headphone Amplifier.
5. MICRO-CONTROLLER CONFIGURATION INTERFACE.
The PA5750 supports standard SPI and 2-wire micro-controller configuration interface. An External micro-
controller can completely configure the PA5750 through writing to internal configuration registers. Chapter 8
describes in detail the configuration of the registers.
The identical pins are used to configure for either SPI or 2-wire interface.
In SPI mode, CE (Pin 30), CCLK (Pin 32) and CDATA (Pin 31) functions as SPI_CSn, SPI_CLK and SPI_DIN.
In 2-wire mode, CE (Pin 30), CCLK (Pin 32) and CDATA (Pin 31) functions as AD0, SCL and SDA respectively.
To select SPI mode, apply a high to low transition signal to CE (pin 30). If no signal is applied, the PA5750 will
operate in 2-wire interface mode.
5.1 SPI
The PA5750 has a SPI (Serial Peripheral Interface) compliant synchronous serial slave controller internal to the
chip. It provides the ability to allow the external master SPI controller to access the internal registers, thereby
controlling the operation of the chip.
All lines on the SPI bus are unidirectional: The SPI_CLK is generated by the master controller and is primarily
used to synchronize DATA transfer; the SPI_DIN line carries DATA from the master to the slave. SPI_CSn is
generated by the master to select the PA5750.
The timing diagram of this interface is given in Fig. 1. The high to low transition at SPI_CSn (pin 30) indicates
the SPI interface selected. Each write procedure contains 3 words, i.e. Chip Address plus R/W bit, internal
register address and internal register DATA. Every word is fixed at 8 bits. The input SPI_DIN DATA is sampled
at the rising edge of SPI_CLK clock. The MSB bit in each word is transferred first. The transfer rate can be up to
10Mbps.
SPI_DIN
SPI_CLK
Chip Address
R/W
7 bits - 0010000
bit
RAM
8 bits
Register DATA
8 bits
0
1
5
6
7
8
9
14
15 16 17
22
23
SPI_CSn
RAM =Register Address Mapping
Fig.1 SPI Configuration Interface Timing Diagram.
5.2 2-wire Interface
2-wire interface is a bi-directional serial BUS that uses a serial data line (SDA) and a serial clock line (SCL) for
DATA transfer. The timing diagram for DATA transfer is given in Fig. 2.
DATA is transmitted synchronously to SCL clock on the SDA line in a byte-by-byte basis. Each bit in a byte is
sampled during SCL high with the MSB bit transferred first. Each transferred byte is followed by an acknowledge
bit from receiver to pull the SDA low.
The transfer rate of the 2-wire interface can be up to 100kbps.
561 E Elliot Road.#175 Chandler, AZ 85225 Tel: [phone]. Fax: [phone].
7
95230 Rev.0. 04/09
www.protekanalog.com
Not for use in any life support systems.