SLVDA28LC Datasheet, PDF (4/5 Pages) Protek Devices – ULTRA LOW CAPACITANCE TVS ARRAY

SLVDA2.8LC
APPLICATION NOTE
Electronic equipment is susceptible to damage caused by Electrostatic Discharge (ESD), Electrical Fast Transients (EFT), and tertiary lightning effects.
Knowing that equipment can be damaged, the SLVDA2.8LC was designed to provide the level of protection required to safe guard sensitive high
speed data circuits. This product can be used to provide a level of protection to meet bidirectional requirements either in a common-mode or
differential-mode configuration.
BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 1)
The SLVDA2.8LC can provide up to four (4) lines of protection in a common-mode configuration as depicted in Figure 1.
Circuit connectivity is as follows:
✔ Line 1 is connected to pin 8
✔ Line 2 is connected to pin 7
✔ Line 3 is connected to pin 6
✔ Line 4 is connected to pin 5
✔ Pins 1, 2, 3, and 4 are connected to ground
Figure 1: Bidirectional Common-Mode Protection
BIDIRECTIONAL DIFFERENTIAL-MODE CONFIGURATION (Figure 2)
The SLVDA2.8LC can provide up to four line pairs (4) of protection in a differential-mode configuration as depicted in Figure 2.
Circuit connectivity is as follows:
✔ Line Pair # 1 is connected to pin 8 and 1
✔ Line Pair # 2 is connected to pin 7 and 2
✔ Line Pair # 3 is connected to pin 5 and 4
✔ Line Pair # 4 is connected to pin 6 and 3
Figure 2: Bidirectional Differential-Mode Protection
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following guidelines
are recommended:
✔ The protection device should be placed near the
input terminals or connectors, the device will divert
the transient current immediately before it can be
coupled into the nearby traces.
✔ The path length between the TVS device and the
protected line should be minimized.
✔ All conductive loops including power and ground
loops should be minimized.
✔ The transient current return path to ground should
be kept as short as possible to reduce parasitic
inductance.
✔ Ground planes should be used whenever possible.
For multilayer PCBs, use ground vias.
05143.R6 4/05
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