PLC497 Datasheet, PDF (4/5 Pages) Protek Devices – ULTRA LOW CAPACITANCE TVS ARRAY

PLC497
APPLICATION NOTE
The PLC497 is an ultra low capacitance, bidirectional array that is designed to protect I/O or high speed data lines from the damaging effects of ESD
or EFT. This product has a surge capability of 250 Watts P_PP per line for an 8/20µs wave form and offers ESD protection > 40kV.
DIFFERENTIAL-MODE CONFIGURATION (Figure 1)
The PLC497 is designed to protect one unidirectional line. Figure 1 shows a typical differential-mode (line to line) I/O port protection circuit applica-
tion. To achieve bidirectional protection, two PLC497 units are placed in parallel with opposing polarities within the circuit layout.
Circuit connectivity is as follows:
✔ Pins 1 and 2 of each device connected to datalines
✔ Pin 3 is not connected
COMMON-MODE CONFIGURATION (Figure 2)
The PLC497 can provide protection for sensor circuit applications. Figure 2 is a typical common-mode (line to ground) sensor circuit application. To
achieve bidirectional protection in this application, a second pair of TVS devices is added in parallel with opposing polarities where pins 2 are
connected to the line, pins 1 connected to ground and pins 3 unconnected.
Circuit connectivity is as follows:
✔ Pins 1 each device connected to datalines
✔ Pins 2 each device connected to ground
✔ Pin 3 is not connected
Figure 1. Typical Differential-Mode i/o Port Protection Circuit
LINE 1 IN
LINE 1 OUT
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following guidelines
are recommended:
✔ The protection device should be placed near the
input terminals or connectors, the device will divert
the transient current immediately before it can be
coupled into the nearby traces.
✔ The path length between the TVS device and the
protected line should be minimized.
✔ All conductive loops including power and ground
loops should be minimized.
✔ The transient current return path to ground should
be kept as short as possible to reduce parasitic
inductance.
✔ Ground planes should be used whenever possible.
For multilayer PCBs, use ground vias.
1
2
LINE 2 IN
3
3
2
1
LINE 2 OUT
Figure 2. Typical Common-Mode Sensor Protection Circuit
SENSOR
1
3
2
2
3
1
CIRCUITRY
1
3
2
2
3
1
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