PT6312_10 Datasheet, PDF (11/21 Pages) Princeton Technology Corp – VFD Driver/Controller IC

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VFD Driver/Controller IC
PT6312
SCANNING AND DISPLAY TIMING
The Key Scanning and display timing diagram is given below. One cycle of key scanning consists of 1
frame. The data of the 6 x 4 matrix is stored in the RAM.
TDISPLAY= 500µs
Key S can D ata
SG Output DIG1
G1
G2
G3
DIG2
DIG3
DIGn
DIG1
Gn
1 Frame = TD ISPLAY x (n +1)
PT6312 V2.6
- 11 -
December, 2005