EPR-000008 Datasheet, PDF (17/20 Pages) Power Integrations, Inc. – Engineering Prototype Report 1.2 W, Universal Input, Non-isolated, TNY254 (EP8)

23-April-2001
EPR-000008 – 1.2 W Universal Input Non-Isolated TNY254
8.6 Surge Voltage Immunity (2 kV and 6 kV, 1.2/50 ms per IEC1000-4-5)
Two series of surge tests were performed:
Configuration “1” (2 kV), Fig. 8.6.1 and configuration “2” (6 kV), Fig. 8.6.2 passed 20
surges each at 45 seconds apart; 10 surges with positive (Fig. 8.6.3) and 10 with
negative polarity (Fig. 8.6.4), all at high input line and full load. The 45 seconds delay
between surges allows the energy rated components (R1, R2 and RV1) to cool down.
High input line is the worst case condition as the input capacitor (C1) reaches highest
voltage therefore minimizing margin for TinySwitch breakdown voltage.
R2 limits the charging current during a +voltage surge such that C1 peak voltage does
not exceed the TNY254 breakdown voltage.
R1 limits the maximum surge current to approximately 50 A, the value at which the
clamping voltage of the varistor is characterized (<700 V). The 6 kV, 1.2/50 ms pulse at
700 V clipping level is approximately 100 ms (see Fig. 8.7.2). From the graph in Fig. 8.6.5,
it can be inferred that the unit will survive 10 k surges of -6 kV (more of +6 kV as C1 can
divert ~0.3 J).
Reducing the value of R1 would reduce the total number of 6 kV pulses the unit can
survive.
J1-1
L
J1-1
L
85-265 V_AC, 50/60 Hz
C1
6.8 mF ⁺
400 V
J1-3 ^D3
R2
N
1N4007 180 W, 3 W, fusible
D1
1N4007
Figure 8.6.1 - Configuration “1”, 2 kV.
85-265 V_AC, 50/60 Hz RV1
C1 ₊
6.8 mF
400 V
J1-3
R1
R2
N
100 W, surge 180 _W, 3 W, fusible
D1
1N4007
Figure 8.6.2 - Configuration “2”, 6 kV.
Page 17 of 20
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