PS12014-A Datasheet, PDF (6/6 Pages) Powerex Power Semiconductors – FLAT-BASE TYPE INSULATED TYPE

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12014-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.
off
VCIN
on
on
V(hold)
off
N-side IGBT Current
N-side FWDi Current
IC
0
+ICL
(VS)
0
–ICL
Ref
VC
t(hold)
0
off
VCL _on
Delay time
td(read)
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up
High to VDL voltage (OFF level); however, FO1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. FO1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
DC-Bus voltage
VPN ₀
Control voltage supply VDH, DL ₀
Boot-strap voltage
N-Side input signal
VDB ₀
VCIN(N)
on
PWM starts
a)
b)
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
CPU
5.1kΩ
R
R
10kΩ
0.1nF 0.1nF
VDL(5V) _ASIPM
UP,VP,WP,UN,VN,WN,Br
FO1,FO2,FO3,CL
CU,CV,CW
GND(Logic)
P-Side input signal VCIN(P) _on
Brake input signal
FO1 output signal
VCIN(Br) _on
FOI _on
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20µs number of pulses =10 ~ 500 de-
pending on the boot-strap capacitor size)
b) FO1 resetting sequence:
Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order.
Jan. 2000