BG2B-5015 Datasheet, PDF (4/5 Pages) Powerex Power Semiconductors – BG2B – Universal Gate Drive Prototype Board

Interface Circuit Requirements: A typical interface circuit for the BG2B is shown in Figure 4. A single control
power supply (+V_S) is connected to Pin 5 of CN1 with its common at Pin 6. This supply provides all of the gate
drive power for both channels via the hybrid DC-to-DC converters. The current drawn from the +V_S supply will vary
from less than 100mA to more than 500mA depending on the switching frequency and size of IGBT being driven.
Consult the hybrid gate driver application notes for details on determining the required supply current for the gate
driver. The gate driver supply current can then be converted into current drawn from the +V_S supply using the
efficiency specification on the DC-to-DC converter datasheet.
Figure 4: BG2B External Wiring Diagram
A 5V logic supply is connected at Pin 1 of CN1 and shares the same common at Pin 6 of CN1 as the15V
control supply. The 5V supply is directly connected to Pin 14 of the hybrid gate driver which is internally
connected to the anode of the LED in the high speed opto-coupler. The 5V supply is also used to pull the output
side of the fault isolation opto-couplers high. The control signal interface is designed for use with standard 5V
CMOS logic. The control input signals at Pins 2 and 3 of connector CN1 are used to turn the IGBTs on and off.
These signals are active low which means that the gate driver output will be high (IGBT on) when they are pulled
low. These control pins are connected directly to Pin 13 of the hybrid gate driver which is connected internally
through a 180Ω limiting resistor to the cathode of the LED in the high speed opto-coupler (see Figure 1). W hen the
control signal is pulled low, current flows from the 5V logic supply through the LED to turn the gate driver’s
output on. The control pins must be pulled low with a buffer that is capable of sinking at least 16mA in order to
turn on the high speed opto-coupler inside the hybrid gate driver. A CMOS buffer that actively pulls its output high
in the off state (74HC04 or similar) is recommended for maintaining good common mode noise immunity. Open
collector drive that allows IN1 and IN2 to float will degrade common mode noise immunity and is therefore not
recommended.
The fault signal line on Pin 4 of CN1 is active low which means that a fault condition will be indicated by a low level
signal. During normal operation Pin 4 is pulled high to the +V_L supply by the 4.7K resistor R3. If either of the
hybrid gate drivers detects a short circuit condition, its fault isolation opto (OP1, OP2) will turn on and pull Pin 4
of CN1 low. W hen a fault is detected the hybrid gate drivers disable the output and produce a fault signal for a
minimum of 1ms. Any signal on the fault line that is significantly shorter than 1ms cannot be a legitimate fault so it
should be ignored. Therefore, for a robust noise immune design, it is recommended that an RC filter with a time
constant of approximately 10μs be added between Pin 4 and the controller as shown in Figure 4.
Publication Date: 02-03-2016
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Rev. 1