BG2A Datasheet, PDF (4/5 Pages) Powerex Power Semiconductors – Universal Gate Drive Prototype Board

Figure 3: BG2A External Wiring Diagram
To logic
level
control
circuits
RC Filter to remove
noise on fault signal
RC~10µs
CMOS type buffer
must sink 15mA
CN1
GND
+VS
FO
IN1
IN2
+VL
1
1
G
E
C
CN2
1
G
E
C
CN3
C1
G1
E1
C2E1
G2
E2
E2
IGBT Module
VLA500 series driver. A CMOS buffer that actively pulls its output high is recommended for maintaining good
common mode noise immunity in the off state. Open collector type drive is not recommended.
The fault signal line on pin 4 of CN1 is active low which means that a fault condition will be indicated by
a low level signal. During normal operation pin 4 is pulled high to the +5V supply (+V_L) by the 4.7K resistor R3.
If either of the VLA500 series gate drivers detects a short circuit condition the fault isolation optos (OP1, OP2)
turn on and pull pin 4 of CN1 low. When a fault is detected the hybrid gate drivers disable the output and
produce a fault signal for a minimum of 1ms. Any signal on the fault line that is significantly shorter than 1ms
can not be a legitimate fault so it should be ignored. Therefore, for a robust noise immune design, it is
recommended that an RC filter with a time constant of approximately 10µs be added between pin 4 and the
controller as shown in figure 3.
Printed Circuit Layout: Figure 4 shows the layout of the BG2A two channel gate driver board. The
compact 2” x 4” circuit board with only 24 components clearly demonstrates the advantage of using the VLA500
Figure 4: BG2A Printed Circuit Board Layout
Component Side Copper
Component Legend
4
Solder Side Copper