PO74HSTL85353A Datasheet, PDF (1/7 Pages) Potato Semiconductor Corporation – The PO74HSTL85353A is a low-skew, 1-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications.

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PO74HSTL85353A
LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer
300MHz HSTL Potato Chip
FEATURES:
DESCRIPTION:
. Patented Technology
. Four HSTL differential outputs
. Two single LVTTL/LVCMOS inputs
(selectable LVCMOS/ LVTTL clock or crystal input)
. Operating frequency up to 300MHz with 15pf load
. Very low output pin to pin skew < 50ps
. 3.4-ns propagation delay (max)
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin TSSOP package
The PO74HSTL85353A is a low-skew, 1-to-4 differential
fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications.
The device is implemented on CMOS technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to
300MHz .
The device features two inputs, one is LVTTL / LVCMO
signal and the other is crystal input. This mux is
controlled by the CLK_SEL pin. The PO74HSTL85353A
functions as a signal-level translator and fanout on
LVCMOS / LVTTL single-ended signal to four HSTL
differential loads. Since the PO74HSTL85353A
introduces negligible jitter to the timing budget, it is the
ideal choice for distributing high frequency, high precision
clocks across back-planes and boards in communication
systems.
Pin Configuration
VEE 1
CLK_EN ²
CLK_SEL ³
CLK ⁴
nc 5
XTAL_IN 6
XTAL_OUT 7
nc 8
nc 9
VCC
10
20 Q0
19 nQ0
18
VCC
17 _Q1
16 nQ1
15 _Q2
14 _nQ2
13
VCC
12 _Q3
11 _nQ3
Logic Block Diagram
CLK_EN ^Pullup
CLK ^Pulldown
0
XTAL_IN
OSC
1
XTAL_OUT
CLK_SEL ^Pulldown
D
Q
LE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Potato Semiconductor Corporation
1
01/01/10