PO74HSTL314A_14 Datasheet, PDF (1/7 Pages) Potato Semiconductor Corporation – 2.3V - 3.6V 2:4 Differential Clock/Data Fanout Buffer

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PO74HSTL314A
2.3V - 3.6V 2:4 Differential Clock/Data Fanout Buffer
500MHz HSTL Potato Chip
FEATURES:
DESCRIPTION:
. Patented Technology
. Four HSTL differential outputs
. The two pair of LVDS/LVPECL/HSTL/ differential
or single-ended inputs
. Hot-swappable/-insertable
. Operating frequency up to 500MHz with 2pf load
. Operating frequency up to 480MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. Very low output pin to pin skew < 80ps
. Very low pulse skew < 80ps
. 2.8-ns propagation delay (typical)
. 2.3V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin 209 mil SSOP package
The PO74HSTL314 is a low-skew, 2-to-4 differential
fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications.
The device is implemented on 0.35um CMOS technology
and has a fully differential internal architecture that is
optimized to achieve low signal skews at operating
frequencies of up to 500MHz .
The device features two differential input paths that are
multiplexed plexed internally. This mux is controlled by
the CLK_SEL pin. The PO74HSTL314 may function not
only as a differential clock buffer but also as a signal-level
translator and fanout on HSTL or LVCMOS / LVTTL
single-ended signal to four HSTL differential loads.
Since the PO74HSTL314 introduces negligible jitter to the
timing budget, it is the ideal choice for distributing high
frequency, high precision clocks across back-planes and
boards in communication systems.
Pin Configuration
Logic Block Diagram
Q0
VCC
VCC 1
20 VCC
Q0#
NC ²
19 _Q0
CLKA
CLKA#
VCC ³
18 Q0#
Q1
Q1#
CLK_SEL
4
CLKA ⁵
17 _Q1
16 Q1#
VCC
Q2
CLKA# ⁶
CLKB ⁷
15 _Q2
14 _Q2#
CLKB
CLKB#
CLKB# ⁸
13 _Q3
Q2#
Q3
Q3#
GND ⁹
12 _Q3#
CLK_SEL
VCC ¹⁰
11 _VCC
Potato Semiconductor Corporation
1
01/01/10