PO74HSTL314A Datasheet, PDF (1/7 Pages) Potato Semiconductor Corporation – 3.3V 2:4 Differential Clock/Data Fanout Buffer

PO74HSTL314A
3.3V 2:4 Differential Clock/Data Fanout Buffer
500MHz HSTL Potato Chip
07/28/06
FEATURES:
DESCRIPTION:
. Patented Technology
. Four HSTL differential outputs
. The two pair of LVDS/LVPECL/HSTL/ differential
or single-ended inputs
. Hot-swappable/-insertable
. Operating frequency up to 500MHz with 2pf load
. Operating frequency up to 480MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. Very low output pin to pin skew < 80ps
. Very low pulse skew < 80ps
. 2.8-ns propagation delay (typical)
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin 209 mil SSOP package
The PO74HSTL314 is a low-skew, 2-to-4 differential
fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications.
The device is implemented on 0.35um CMOS technology
and has a fully differential internal architecture that is
optimized to achieve low signal skews at operating
frequencies of up to 500MHz .
The device features two differential input paths that are
multiplexed plexed internally. This mux is controlled by
the CLK_SEL pin. The PO74HSTL314 may function not
only as a differential clock buffer but also as a signal-level
translator and fanout on HSTL or LVCMOS / LVTTL
single-ended signal to four HSTL differential loads.
Since the PO74HSTL314 introduces negligible jitter to the
timing budget, it is the ideal choice for distributing high
frequency, high precision clocks across back-planes and
boards in communication systems.
Pin Configuration
VCC 1
NC ²
VCC ³
CLK_SEL
4
CLKA ⁵
CLKA# ⁶
CLKB ⁷
CLKB# ⁸
VEE ⁹
VCC ¹⁰
20 VCC
19 _Q0
18 Q0#
17 _Q1
16 Q1#
15 _Q2
14 _Q2#
13 _Q3
12 _Q3#
11 _VCC
Logic Block Diagram
VCC
Q0
Q0#
CLKA
CLKA#
Q1
Q1#
VEE
VCC
Q2
CLKB
Q2#
CLKB#
Q3
VEE
Q3#
CLK_SEL
VEE
1
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