PO74G74A_14 Datasheet, PDF (1/6 Pages) Potato Semiconductor Corporation – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

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PO54G74A, PO74G74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
54, 74 Series Noise Cancellation GHz Logic
FEATURES:
. Patented technology
. Specified From –40°C to 125°C, –55°C to 125°C
. Operating frequency is faster than 600MHz
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 14pin 150mil wide SOIC package
. Available in 14pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
DESCRIPTION:
Potato Semiconductor’s PO74G74A is designed for
world top performance using submicron CMOS
technology to achieve higher than 600MHz TTL
/CMOS output frequency with less than 2ns propaga-
tion delay.
This dual D flip-flop is designed for 1.65-V to 3.6-V
VCC operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1CLR 1
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
GND 7
14 ^VCC
13 2CLR
12 ^2D
11 2CLK
10 2PRE
9 2Q
8 2Q
Pin Description
INPUTS
PRE CLR CLK
D
L
H
X
X
H
L
X
X
L
L
X
X
H
H
H
H
H
L
H
H
L
X
OUTPUTS
Q
Q
H
L
L
H
L
L
H
L
L
H
Q₀
Q₀
Potato Semiconductor Corporation
1CLK
NC
1PRE
NC
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2D
NC
2CLK
NC
2PRE
Logic Block Diagram
1CLR 1
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
GND 7
PRE
D
Q
1
Q
CLR
PRE
D
Q
2
Q
CLR
14 Vcc
13 2CLR
12 2D
11 2CLK
10 2PRE
9 2Q
8 2Q
1
01/01/10