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PO74G164245A Datasheet, PDF (1/9 Pages) Potato Semiconductor Corporation – 1.65v-3.6v, 16-bit Dual Supply Level Shifting Bidirectional Transceiver with 3 state outputs
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PO74G164245A
1.65v-3.6v, 16-bit Dual Supply Level Shifting
Bidirectional Transceiver with 3 state outputs
74 Series Noise Cancellation GHz Logic
FEATURES:
. Patented technology
. Operating frequency up to 1GHz with 2pf load
. VCC Operates from 1.65V to 3.6V
. Low input capacitance: 5pf typical
. Available in 48pin TSSOP package
. Comparator A inputs for accuracy signals
Pin Configuration
1DIR 1
1B0 2
1B1 3
GND 4
1B2 5
1B3 6
VCCB1 7
1B4 8
1B5 9
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
VCCB2 18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCCA1
41 1A4
40 1A5
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2B2
32 2A3
31 VCCA2
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
DESCRIPTION:
Potato Semiconductor’s PO74G164245A is designed
for world top performance using submicron CMOS
technology to achieve 1GHz TTL /CMOS output
frequency.This Octal bus buffer gate is designed for
1.65v-3.6v, 16-bit Dual Supply Level ShiftingBidirec-
tional Transceiver with 3 state outputs operation.
Contains two separate supply rails: B port (VCCB)
must set higher voltage (equal) then A port
(VCCA).This arrangement permits translation from a
1.8-2.5V to 3.3V environment.
The PO74G164245A features independent 16-bit
Bidirectional Transceiver with 3 state outputs. Each
output is disabled when the associated output-
enable(OE) input is high.
Logic Block Diagram
VCCA1
VCCA2
44k 1DIR
2DIR
44k
(Typ.)
1OE (Typ.)
2OE
1A0
1B0
2A0
2B0
1A1
1B1
2A1
2B1
1A2
1B2
2A2
2B2
1A3
1B3
2A3
2B3
1A4
1B4
2A4
2B4
1A5
1B5
2A5
2B5
1A6
1B6
2A6
2B6
44k 1A7
(Typ.)
1B7
44k 2A7
(Typ.)
2B7
Pin Description
Pin Name
xOE
xDIR
XAX
XBX
GND
VCC
Description
3-State Output Enable Inputs (Active LOW)
Direction Control Input
Side A Inputs or 3-State Inputs
Side B Outputs or 3-State Outputs
Ground
Power
Potato Semiconductor Corporation
Truth Table
Inputs
xOE
xDIR
L
L
L
H
H
X
xDIR
X
L
H
VCCAx
0V
X
>0V
1
Outputs
Bus B Data to Bus A
Bus A Data to Bus B
Z
Comparator InputAx
disable
disable
Enable
01/01/10