PO74G16244_14 Datasheet, PDF (1/5 Pages) Potato Semiconductor Corporation – 16-BIT BUFFER / LINE DRIVERS WITH 3-STATE OUTPUTS

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PO74G16244A
16-BIT BUFFER / LINE DRIVERS WITH 3-STATE OUTPUTS
74 Series Noise Cancellation GHz Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 300MHz with 15pf load
. Operating frequency up to 100MHz with 50pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 48pin TSSOP package
Potato Semiconductor’s PO74G16244A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This Octal bus buffer gate is designed for 1.65-V to
3.6-V VCC operation.
The PO74G16244A features independent line driver
swith 3-state outputs. Each output is disabled when the
associated output- enable(OE) input is high.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1OE 1
1Y1 2
1Y2 3
GND 4
1Y3 5
1Y4 6
V_CC 7
2Y1 8
2Y2 9
GND 10
2Y3 11
2Y4 12
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
V_CC 18
4Y1 19
4Y2 20
GND 21
4Y3 22
4Y4 23
4OE 24
48 2OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 V_CC
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
31 V_CC
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3OE
Logic Block Diagram
1OE ¹
1A1 ⁴⁷
1A2 ⁴⁶
1A3 ⁴⁴
1A4 ⁴³
2OE ⁴⁸
2A1 ⁴¹
2A2 ⁴⁰
2A3 ³⁸
2A4 ³⁷
2 _1Y1
3 _1Y2
5 _1Y3
6 _1Y4
3OE ²⁵
3A1 ³⁶
3A2 ³⁵
3A3 ³³
3A4 ³²
8 _2Y1
9 _2Y2
11 _2Y3
12 _2Y4
4OE ²⁴
4A1 ³⁰
4A2 ²⁹
4A3 ²⁷
4A4 ²⁶
13 _3Y1
14 _3Y2
16 _3Y3
17 _3Y4
19 _4Y1
20 _4Y2
22 _4Y3
23 _4Y4
Pin Description
INPUTS
OE
A
L
H
L
L
H
X
OUTPUT
Y
H
L
Z
Potato Semiconductor Corporation
1
01/01/10