PO74G16240A_14 Datasheet, PDF (1/5 Pages) Potato Semiconductor Corporation – 16-Bit Inverting Buffer/ Driver with 3-State Outputs

www.potatosemi.com
PO74G16240A
16-Bit Inverting Buffer/ Driver with 3-State Outputs
74 Series Noise Cancellation GHz Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 300MHz with 15pf load
. Operating frequency up to 100MHz with 50pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 48pin TSSOP package
Potato Semiconductor’s PO74G16240A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This Octal bus buffer gate is designed for 1.65-V to
3.6-V VCC operation.
The PO74G16240A features independent line driver
swith 3-state outputs. Each output is disabled when the
associated output- enable(OE) input is high.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1OE
1
1Y1
2
1Y2
3
GND
4
1Y3
5
1Y4
6
VCC
7
2Y1
8
2Y2
9
GND
10
2Y3
11
2Y4
12
3Y1
13
3Y2
14
GND
15
3Y3
16
3Y4
17
VCC
18
4Y1
19
4Y2
20
GND
21
4Y3
22
4Y4
23
4OE
24
48
2OE
47
1A1
46
1A2
45
GND
44
1A3
43
1A4
42
VCC
41
2A1
40
2A2
39
GND
38
2A3
37
2A4
36
3A1
35
3A2
34
GND
33
3A3
32
3A4
31
VCC
30
4A1
29
4A2
28
GND
27
4A3
26
4A4
25
3OE
Logic Block Diagram
1OE ¹
1A1 ⁴⁷
46
1A2
44
1A3
43
1A4
2OE ⁴⁸
41
2A1
40
2A2
38
2A3
37
2A4
2 _1Y1
3OE ²⁵
3A1 ³⁶
3
1Y2
35
3A2
5
1Y3
33
3A3
6
1Y4
32
3A4
8 _2Y1
9 _2Y2
11 _2Y3
12 _2Y4
24
4OE
30
4A1
29
4A2
27
4A3
26
4A4
13 _3Y1
14
3Y2
16
3Y3
17
3Y4
19
4Y1
20
4Y2
22
4Y3
23
4Y4
Truth Table
Inputs
nOE
nAX
L
L
L
H
H
X
Outputs
nYx
H
L
Z
Potato Semiconductor Corporation
1
01/01/10