PO74G139A_14 Datasheet, PDF (1/6 Pages) Potato Semiconductor Corporation – DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER

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PO74G139A
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER
74 Series Noise Cancellation GHz Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 800MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.7ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 16 pin SOIC package
Potato Semiconductor’s PO74G139A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.7ns propagation delay.
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
The PO74G139A comprises two individual 2-line to
4-line decoders in a single package. Theactive-
lowenable (G) input can be used as a data line in
demultiplexing applications. This decoder/ demulti-
plexer features fully buffered
inputs, each of which represents only one normalized-
load to itsdriving circuit.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1G ¹
1A ²
1B ³
1Y0 ⁴
1Y1 ⁵
1Y2 6
1Y3 7
GND ⁸
16 _VCC
15 2G
14 _2A
13 2B
12 2Y0
11 2Y1
10 2Y2
9 2Y3
1G ¹
Select
Inputs
1A ²
1B ³
2G ¹⁵
Select
Inputs
2A ¹⁴
2B ¹³
4 _1Y0
5 _1Y1
6 _1Y2
7
1Y3
12 _2Y0
11 _2Y1
10 _2Y2
Data
Outputs
9 _2Y3
Pin Description
INPUTS
SELECT
G
B
A
L
L
L
L
L
H
L
H
L
L
H
H
H
X
X
OUTPUTS
Y3
Y2
Y1
Y0
H
H
H
L
H
H
L
H
H
L
H
H
L
H
H
H
H
H
H
H
Potato Semiconductor Corporation
1
01/01/10