PO74G125A Datasheet, PDF (1/6 Pages) Potato Semiconductor Corporation – QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

PO74G125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
74 Series GHz Logic
07/26/06
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 550MHz with 5pf load
. Operating frequency up to 300MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G125A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
The PO74G125A features independent line drivers with
3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high. To ensure
the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is
determined by the current-sinking capability of
the driver.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 V C C
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
Pin Description
INPUTS
OE
A
L
H
L
L
H
X
OUTPUT
Y
H
L
Z
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
3
1Y
6
2Y
8
3Y
11
4Y
1
Copyright © 2005-2006, Potato Semiconductor Corporation