PO74G112A_14 Datasheet, PDF (1/6 Pages) Potato Semiconductor Corporation – DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET

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PO74G112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
74 Series Noise Cancellation GHz Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency up to 750MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 16pin 150mil wide SOIC package
. Available in 16pin 173mil wide TSSOP package
Potato Semiconductor’s PO74G112A is designed for
world top performance using submicron CMOS
technology to achieve 750MHz TTL /CMOS output
frequency with less than 2ns propagation delay.
This dual negative-edge-triggered J-K flip-flop is
designed for 1.65-V to 3.6-V VCC operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1CLK ₁
1K 2
1J 3
1PRE 4
1Q 5
1Q 6
2Q 7
GND ⁸
16 ^V_CC
15 1CLR
14 2CLR
13 2CLK
12 2K
11 2J
10 2PRE
9 _2Q
Pin Description
INPUTS
PRE
CLR
CLK
J
K
L
H
X
X
X
H
L
X
X
X
L
L
X
X
X
H
H
L
L
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
X
X
OUTPUTS
Q
Q
H
L
L
H
H
H
Q₀
Q₀
H
L
L
H
Toggle
Q₀
Q₀
Logic Block Diagram
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
PRE
J
Q
1
K
Q
CLR
PRE
J
Q
1
K
Q
CLR
V_CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
Potato Semiconductor Corporation
1
01/01/10