PO74G08A_14 Datasheet, PDF (1/6 Pages) Potato Semiconductor Corporation – QUADRUPLE 2-INPUT POSITIVE-AND GATES

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PO54G08A, PO74G08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES
54, 74 Series Noise Cancellation GHz Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 750MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 14pin 150mil wide SOIC package
. Available in 14pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
Potato Semiconductor’s PO74G08A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input positive-AND gate is designed
for 1.65-V to 3.6-V VCC operation.
The PO74G08A performs the Boolean function
Y= A B or Y= A + B in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as transla-
tors in a mixed 3.3V/5V system environment.
Pin Configuration
1A 1
1B 2
1Y ³
2A 4
2B 5
2Y 6
GND 7
14 V _CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
Pin Description
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
H
L
L
Potato Semiconductor Corporation
1Y
3 2 1 20 19
4
18
4A
NC 5
17 ^NC
2A 6
16 4Y
NC 7
15 NC
2B 8
14 3B
9 10 11 12 13
Logic Block Diagram
A
Y
B
1
01/01/10