PO54G374A Datasheet, PDF (1/6 Pages) Potato Semiconductor Corporation – OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

PO54G374A, PO74G374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
54, 74 Series GHz Logic
10/27/07
FEATURES:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency is faster than 600MHz
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2.4ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 20pin TSSOP package
. Available in 20pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
DESCRIPTION:
Potato Semiconductor’s PO74G374A is designed for
world top performance using submicron CMOS
technology to achieve higher than 600MHz TTL
/CMOS output frequency with less than 2.4ns
propagation delay.
This dual Octal edge triggered D-type flip-flops are
designed for 1.65-V to 3.6-V VCC operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
Pin Description
INPUTS
OE LE
D
L
H
H
L
H
L
L
L
X
H
X
X
OUTPUT
Q
H
L
Q₀
Z
3 2 1 20 19
2D ₄
18 ^8D
2Q ₅
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
Logic Block Diagram
1
OE
11
LE
C1
3
1D
1D
2
1Q
To Seven Other Channels
1
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