PO100HSTL180A Datasheet, PDF (1/8 Pages) Potato Semiconductor Corporation – Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator

PO100HSTL180A
Differential LVDS/LVPECL/HSTL to LVTTL Translator
LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
FEATURES:
DESCRIPTION:
• Patented Technology
• Differential LVDS/LVPECL/HSTL to LVTTL
Translator
- Operating frequency up to 1GHz with 2pf load
- Operating frequency up to 800MHz with 5pf load
- Operating frequency up to 450MHz with 15pf load
- Very low output pin to pin skew < 150ps
- Propagation delay < 1.8ns max with 15pf load
• LVTTL/LVCMOS to Differential HSTL Translator
- Operating frequency up to 1.65GHz with 5pf load
- Operating frequency up to 500MHz with 15pf load
- Very low output pin to pin skew < 100ps
- Propagation delay < 1.4ns max with 15pf load
• 2.4V to 3.6V power supply
• Industrial temperature range: –40°C to 85°C
• Available in 14-pin 150ml SOIC package
Potato Semiconductor’s PO100HSTL180A is
designed for world top performance using
submicron CMOS technology to achieve 1GHz
LVTTL output frequency with less than 1.8ns
propagation delay and 1.65GHz HSTL output
frequency with less than 1.4ns propagation delay.
The PO100HSTL180A is a low-skew, The small
outline 14 pin package and the low skew design to
make it ideal for applications which require the
translation of a clock or a data signal.
Pin Configuration
Logic Block Diagram
NC ₁
R₂
RE ₃
DE ₄
D₅
GND ₆
GND 7
14 ^V_CC
13 ^V_CC
12 ^A
11 ^B
10 ^Z
9^Y
8 NC
5
D
4
DE
3
RE
2
R
9
Y
10
Z
12
A
11
B
Pin Description
RECEIVER INPUTS
V_ID = V_A– V_B
RE
V_ID ≥ 10 mV
L
10 mV < V_ID < 10 mV
L
V_ID ≤ –10 mV
L
Open
L
X
H
RECEIVER OUTPUT
R
H
?
L
H
Z
DRIVER INPUTS
D
DE
L
H
H
H
Open
H
X
L
DRIVER OUTPUTS
Y
Z
L
H
H
L
L
H
Z
Z
1
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