PM5371TUDX Datasheet, PDF (83/93 Pages) PMC-Sierra, Inc – SONET/SDH TRIBUTARY UNIT CROSS CONNECT

DATA SHEET
PMC-920525
ISSUE 6
PM5371 TUDX
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
Figure 18 - Microprocessor Interface Write Access Timing For Motorola
Mode
A[4:0]
RWB
ALE
(!CS1B&!CS2B&E)
D[7:0]
tS _AW
Valid Address
tS _RWB
tH _RWB
tS _ALW
tV _L
tS _LW
tH _ALW
tH _LW
tV _WR
tH _AW
tS _DW
tH _DW
Valid Data
Notes on Microprocessor Interface Write Timing In Motorola Mode:
1. A valid write cycle is defined as a logical AND of the inverted CS1B, inverted
CS2B and the E signal when RWB is low.
2. Microprocessor Interface timing applies to normal mode register accesses
only.
3. In non-multiplexed address/data bus architectures, ALE should be held high,
parameters tS_ALW, tH_ALW, tV_L, and tS_LW are not applicable.
4. Parameters tH_AW and tS_AW are not applicable if address latching is used.
5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
6. When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 75