PM7339 Datasheet, PDF (69/81 Pages) PMC-Sierra, Inc – Quad Cell Delineation Block Device

RELEASED
DATASHEET
PMC-2000313
ISSUE 2
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Register 400H: S/UNI-CDB Master Test
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
W
W
W
W
R/W
W
R/W
Function
Unused
A_TM[9]
A_TM[8]
PMCTST
DBCTRL
IOTST
HIZDATA
HIZIO
Default
X
X
X
X
0
0
0
0
This register is used to enable S/UNI-CDB test features. All bits, except
PMCTST and A_TM[9:8], are reset to zero by a hardware reset of the
S/UNI-CDB. The S/UNI-CDB Master Test register is not affected by a software
reset (via the S/UNI-CDB Identification, Master Reset, and Global Monitor
Update register (006H)).
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-CDB .
While the HIZIO bit is a logic one, all output pins of the S/UNI-CDB except
the data bus and output TDO are held tri-state. The microprocessor interface
is still active. While the HIZDATA bit is a logic one, the data bus is also held
in a high-impedance state which inhibits microprocessor read cycles. The
HIZDATA bit is overridden by the DBCTRL bit.
IOTST:
The IOTST bit is used to allow normal microprocessor access to the test
registers and control the test mode in each TSB block in the S/UNI-CDB for
board level testing. When IOTST is a logic one, all blocks are held in test
mode and the microprocessor may write to a block's test mode 0 registers to
manipulate the outputs of the block and consequentially the device outputs
(refer to the "Test Mode 0 Details" in the "Test Features" section).
DBCTRL:
The DBCTRL bit is used to pass control of the data bus drivers to the CSB
pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST
are logic one, the CSB pin controls the output enable for the data bus. While
the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-CDB to
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