PM5344SPTX Datasheet, PDF (61/212 Pages) PMC-Sierra, Inc – SONET/SDH PATH TERMINATING TRANSCEIVER TELECOM

DATA SHEET
PMC-930531
ISSUE 6
PM5344 SPTX
SONET/SDH PATH TERMINATING TRANSCEIVER
DISV1:
When set high, the DISV1 bit configures the DC1J1V1, GC1J1V1, and
TC1J1V1 outputs to mark only the frame and synchronous payload envelope
(virtual container) alignments (C1 and J1 bytes). DC1J1V1, GC1J1V1, and
TC1J1V1 will not indicate the tributary multiframe alignment. When DISV1 is
set low, DC1J1V1, GC1J1V1, and TC1J1V1 mark all three of the frame,
payload envelope and tributary multiframe alignments.
Reserved:
The Reserved register bit must be written to logical low for correct operation
of the SPTX.
EXTPT:
When set high, the EXTPT bit configures the SPTX to operate in external
path termination mode. The internal receiver path overhead processor is
disabled. The receive data is taken from the RECEIVE bus. Transport
overhead and payload bytes are distinguished by the RPL input. Frame and
SPE alignment are identified by the RC1J1V1 input. Performance monitoring
related to the incoming pointer and the path overhead column is disabled.
When EXTPT is set low, the internal path overhead processor terminates the
path of the receive stream. Inputs RPL and RDP are ignored.
MONRS:
When set high, the MONRS selects the receive side pointer justification
events counters to monitor the receive stream directly. When MONRS is set
low, the counters accumulates pointer justification events on the DROP bus.
RESBYP:
When set high, the RESBYP bits forces the elastic store in the Receive
Telecombus Aligner to be bypassed. The DROP bus stream will be
synchronous to the receive stream. The DCK input will be ignored and
circuitry timed by DCK will be clocked by PICLK. The transport frame on the
DROP bus will be locked to the receive stream and the DFP input is ignored.
RESBYP must be set low when EXTPT is set high.
TESBYP:
When set high, the TESBYP bits forces the elastic store in the Transmit
Telecombus Aligner to be bypassed. The transmit stream will be synchronous
to the ADD bus. The TCK input will be ignored and circuitry timed by TCK will
be clocked by ACK. The transport frame in the transmit stream will be locked
to that on the ADD bus and the TFP input is ignored.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 47