PM5312STTX Datasheet, PDF (56/140 Pages) PMC-Sierra, Inc – SONET/SDH TRANSPORT OVERHEAD TERMINATING TRANSCEIVER TELECOM STANDARD PRODUCT

DATA SHEET
PMC-930829
ISSUE 5
PM5312 STTX
SONET/SDH TRANSPORT TERMINATING TRANSCEIVER
Address 04H: TLOP Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
UBT
APSREG
DZ2
DAPS
DDL
DOW
FERF
Default
X
0
0
0
0
0
0
0
FERF:
The FERF bit controls the insertion of transmit line far end receive failure
(FERF). When FERF is a logic one, line FERF is inserted into the
SONET/SDH stream on TOUT[7:0]. Line FERF is inserted by transmitting the
code 110 in bit positions 6, 7, and 8 of the K2 byte. Line FERF may also be
inserted using the TFERF input (when the ring control ports are disabled) or
using the transmit ring control port (when it is enabled). When FERF is logic
zero, bit 6, 7, and 8 of the K2 byte are not modified by the transmit line
overhead processor.
DOW:
The DOW bit controls the overwriting of the express orderwire byte (E2).
When DOW is logic one, the value sampled on TIN1[7:0] during the E2 byte
position is passed through the transmit line overhead processor unaltered, as
though the TDIS input had been sampled high during the E2 byte position in
the incoming frame. The upstream insertion of the express orderwire is thus
accomplished without the use of the TDIS input. Note that only the E2 byte
position is passed unaltered, the remaining 2 (STS-3/STM-1) or 11 (STS-
12/STM-4) undefined byte positions are overwritten with all zeros. This
overwriting may be defeated by using the TDIS input, or by using the UBT bit
in this register. When DOW is logic zero, the express order wire source is
nominally the TLOW input (while TDIS and TTOHEN are both low).
DDL:
The DDL bit controls the overwriting of the line data communications channel
(D4 - D12). When DDL is logic one, the values sampled on TIN1[7:0] during
the D4 - D12 byte positions are passed through the transmit line overhead
processor unaltered, as though the TDIS input had been sampled high during
the D4 - D12 byte positions in the incoming frame. The upstream insertion of
the line DCC is thus accomplished without the use of the TDIS input. Note
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