RM5261 Datasheet, PDF (26/40 Pages) PMC-Sierra, Inc – RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Released

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
4 Pin Descriptions
The following is a list of interface, interrupt, and miscellaneous pins available on the RM5261.
Table 5 System Interface
Pin Name Type
ExtRqst*
Input
Release*
Output
RdRdy*
WrRdy*
Input
Input
ValidIn*
Input
ValidOut*
Output
SysAD[63:0] Input/Output
SysADC[7:0] Input/Output
SysCmd[8:0] Input/Output
SysCmdP
Input/Output
Description
External Request
Signals that the system interface is submitting an external request.
Release interface
Signals that the processor is releasing the system interface to slave
state.
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write
request.
Valid Input
Signals that an external agent is now driving a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
Valid Output
Signals that the processor is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd bus.
System Address/Data bus
A 64-bit address and data bus for communication between the
processor and an external agent.
System Address/Data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data
cycles.
System Command/Data identifier bus
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
Reserved for system command/data identifier bus parity
For the RM5261, unused on input and zero on output.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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Document ID: PMC-2002241, Issue 1