PM3386 Datasheet, PDF (24/315 Pages) PMC-Sierra, Inc – Dual Gigabit Ethernet Controller

RELEASED
DATASHEET
PMC-1991129
ISSUE 7
PM3386
DUAL GIGABIT ETHERNET CONTROLLER
Pin Name
RXSD1
TXD0+
TXD0-
TXD1+
TXD1-
ATP0
ATP1
Type Pin No. Function
Input
J25
Differential U26
PECL
Output
U25
Differential M25
PECL
Output
M26
Bi-
M24
Directional
CMOS
M23
Receive Signal Detect (Port 1)
RXSD1 indicates the presence of valid
receive signal power from the Optical
Physical Medium Dependent Device. A
logic level high indicates the presence of
valid data. A logic low indicates a loss of
signal.
Transmit Differential Data (Port 0)
The PECL outputs TXD0+/- contain the
1.25 Gbit/s transmit stream. The TXD0+/-
outputs are driven using the CSU clock.
Transmit Differential Data (Port 1)
The PECL outputs TXD1+/- contain the
1.25 Gbit/s transmit stream. The TXD1+/-
outputs are driven using the CSU clock.
Receive and Transmit Analog Test Ports
The ATP[1:0] pins are used for
manufacturing testing only and should be
tied to analog ground.
Table 3
-Gigabit Media Independent Interface (GMII)
Signal Name
GTX_CLK0
TXD0[0]
TXD0[1]
TXD0[2]
TXD0[3]
TXD0[4]
TXD0[5]
TXD0[6]
TXD0[7]
Direction
Output
Output
Pin No.
AD22
W24
W23
W25
W26
Y24
Y25
AA24
AA25
Function
GMII Transmit Clock (Port 0)
125 MHz reference clock supplied by the
PM3386.
GMII Transmit Data (Port 0)
Byte-wide transmit data is output on these
pins synchronously to the PHY device.
The least significant bit, TXD0[0] is the first
bit transferred on the line.
This signal is updated on the rising edge of
GTX_CLK0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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