PM7383 Datasheet, PDF (208/231 Pages) PMC-Sierra, Inc – FRAME ENGINE AND DATA LINK MANAGER 32A256

RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
significant three bits provide the device address and the least significant ten bits
provide the channel address. Poll results are returned on the TPAn[2:0] signals.
The TPAn[0] bit indicates whether or not space exists in the channel FIFO for
data (high means space exists in the channel FIFO) and the TPAn[1] bit indicates
whether or not that polled channel FIFO is at risk of underflowing and should be
provided data soon (high means the channel FIFO is at risk of underflowing).
The TPAn[2] bit indicates whether or not an underflow condition has occurred on
the polled channel FIFO (high means an underflow condition occurred on that
channel). In Figure 28, channel 55 in device 0 reports that space does not exist
for data in the channel FIFO, that there is currently no risk of underflow on that
channel (hungry) and that an underflow event has not occurred on this channel
since the last poll. Channel 0 in device 0 reports that space exists for data in the
channel FIFO, that there is currently a risk of underflow on that channel (starving)
and that an underflow event has occurred on this channel since the last poll.
Polled results for two channels provide a two fold increase in the polling
bandwidth on the Tx APPI to accommodate the high density of 256 channels.
12.7 BERT Interface
The timing relationship between the receive link clock and data (RCLK[n] / RD[n])
and the receive BERT port signals (RBCLK / RBD) is shown in Figure 29. BERT
is not supported for H-MVIP links. For non H-MVIP links, the selected RCLK[n] is
placed on RBCLK after an asynchronous delay. The selected receive link data
(RD[n]) is sampled on the rising edge of the associated RCLK[n] and transferred
to RBD on the falling edge of RBCLK.
Figure 29 – Receive BERT Port Timing
RCLK[n]
RD[n]
RBCLK
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
RBD
B1 B2 B3 B4
B5
B6 B7 B8 B1
The timing relationship between the transmit link clock and data (TCLK[n] / TD[n])
and the transmit BERT port signals (TBCLK / TBD) is shown in Figure 30. BERT
is not supported for H-MVIP links. TCLK[n] is shown to have an arbitrary
gapping. When TCLK[n] is quiescent, TBD is ignored (X in Figure 30). The
PROPRIETARY AND CONFIDENTIAL
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