PM7323 Datasheet, PDF (206/219 Pages) PMC-Sierra, Inc – ROUTING CONTROL, MONITORING, & POLICING 200 MBPS

STANDARD PRODUCT
PM7323 RCMP-200
DATASHEET
PMC-960543
ISSUE 2
ROUTING CONTROL, MONITORING, & POLICING
200 MBPS
Figure 23 - Microprocessor Interface Write Timing
A[6:0]
ALE
(CSB+WRB)
D[15:0]
Valid Address
tS_ALW
tV_L
tS_LW
tH _ALW
tH_LW
tS_AW
tV_WR
tH _AW
tS _DW
tH _DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB
signals.
2. Microprocessor Interface timing applies to normal mode register accesses
only.
3. In non-multiplexed address/data bus architecture's, ALE should be held high,
parameters tS_ALW, tH_ALW, tV_L, and tS_LW are not applicable.
4. Parameter tH_AW is not applicable if address latching is used.
5. When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
Proprietary and Confidential to PMC-Sierra, Inc.
195
and for its Customer’s Internal Use.